Sampath Balivada
Sampath Balivada

Sampath Balivada

Harvard and von Neumann Architecture - Nand2Tetris

Harvard and von Neumann Architecture - Nand2Tetris

There's a subtle difference.

Sampath Balivada's photo
Sampath Balivada

Published on Nov 4, 2021

2 min read

Some of the quotes and information are part of the Nand2Tetris course available on Coursera.

von Neumann architecture

Let's think from a normal standpoint where we have a single memory device that both stores the program that we need to execute and also stores the data for the program during execution. There are two cycles in this operation. Since we can only operate once on the memory per clock cycle, we have to execute an instruction in 2 cycles.

The two cycles would be:

  1. Fetch Cycle: we probe the memory for the instruction we will be executing.
  2. Execute Cycle: once we have the instruction, we operate on the memory to store and retrieve the data required for the instruction.

This is how von Neumann Architecture handles instruction fetching and execution - in two cycles.

Harvard Architecture

To overcome this limitation of using 2 cycles, the Harvard Mark I relay-based computer, stored instructions on punched tape (the ROM) and data in electro-mechanical counters (or in other words, the RAM).

That's where the architecture got its name from - Harvard Architecture.

Why is this better? The CPU can access both the instruction to execute and also the data required to execute the instruction in the same cycle. So, for something that needs 48 clock cycles to execute, we can finish it in 24 clock cycles. This is quite advantageous and saves time but it's costlier as we need to maintain two memory devices instead of one.

What architecture does my CPU follow?

CPUs that are currently in use implement a modified version of the Harvard Architecture, which is called as, lo and behold, Modified Harvard Architecture. The most significant modification is the use of a split-cache where we implement memory hierarchy and store the instructions in separate data and instruction memory at low levels. The modification is that, instead of having 2 address spaces, one for instructions and one for data, we use single address space.

 
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